1. Technical Field
The present disclosure relates to a method of fabricating an integrated circuit on a semiconductor chip. In particular, the disclosure relates to a method comprising steps of designing an architecture of an integrated circuit comprising at least first and second standard cells implementing a same basic function, designing an integrated circuit layout corresponding to the integrated circuit architecture, and fabricating the integrated circuit according to the integrated circuit layout.
2. Description of the Related Art
Different techniques are known to design and fabricate integrated circuits. The most commonly used technique in the industry is the so-called “cell-based method”, according to which an integrated circuit is seen as a combination of “standard cells”, typically comprising one or more transistors, each implementing a basic function. A standard cell may be a logic gate, a memory cell, or may implement a more complex function (flip-flop, adder, multiplexor, etc.). In general, a standard cell comprises the following information: a functional description of the basic function (such as a truth table); a transistor netlist detailing the cell inputs, outputs, and connections between transistors; and a two-dimensional topographic view or “layout” of the cell as it will be fabricated.
The layout of a standard cell comprises a plurality of polygons of different materials (doped silicon, polysilicon, metal, etc.) situated on different levels and interconnections therebetween. The functioning of the cell is defined by the relative arrangement of the polygons and their interactions. Such a cell layout is designed so that the cell may be reliably fabricated yet still meet performance requirements such as size and speed. Design rules typically define the minimum dimensions of and the spacings between polygons on a same level, as well as the overlap between polygons situated on different levels (corresponding to the thickness of a dielectric layer separating the polygons arranged on different levels). A set of design rules is generally specific to a determined semiconductor fabrication process. Once a standard cell has been designed, it is stored in a cell library. For a given basic function, the library may comprise two or more standard cell layouts, each optimized for different parameters such as area, power consumption and speed.
Therefore, when an integrated circuit architecture has been designed, the corresponding integrated circuit layout is then generated by selecting from the library the standard cells corresponding to the different basic functions, for each basic function that the IC comprises. In some cases, two or more layouts are available for a given basic function, each layout corresponding to a specific set of parameters, for instance one wherein the cell area is optimized, another wherein the speed is optimized, and another wherein the power consumption is optimized. In that case, one cell layout is chosen depending on the desired set of parameters and is used for all instances of the basic function. The cell layouts are placed in rows and their inputs and outputs are routed using a chip netlist defining the interconnections between the different cells.
Reverse engineering is commonly used to find out how an integrated circuit was fabricated, how it works, and the data it contains. In order to reverse engineer an integrated circuit, a library of the different standard cell layouts present in the integrated circuit is first built. The repetition of standard cells greatly reduces the amount of time and effort needed to identify the cell layouts. For example, for an integrated circuit comprising 100,000 cells involving 100 different standard cells, the reverse engineer only has to identify the layout of the 100 different standard cells. Then, an automatic pattern recognition method is used to identify repeat instances of the same cell layout, find the interconnections between the standard cells, and discover the functionalities of the integrated circuit.
U.S. Pat. No. 6,064,110 discloses a method for protecting an integrated circuit from reverse engineering techniques using automatic pattern recognition by designing each cell with a common layout, whatever the basic function implemented by the cell layout. The common layout comprises operative and non-operative connections within and between transistors, signal inputs, and signal outputs. For example, a NAND cell and a NOR cell have the same layout, each comprising PMOS transistors and NMOS transistors and the same apparent interconnections between the transistors. Automatic pattern recognition of the basic functions is thus prevented and the reverse engineer is forced to do a cross-sectional view of each transistor to identify its operative and non-operative connections, and thereby determine the actual basic function implemented by the cell.
However, making all the cells similar, as well as accommodating the operative and non-operative interconnections, has an impact on the timing properties and/or size of the cell, rendering the cell slower and/or larger in terms of surface area occupied. Furthermore, the non-operative interconnections, implemented by implants of opposite dopants, are not compatible with some fabrication technologies using salicides to create metal polygons on the active polygons.
It may be desired therefore to provide an alternate method of fabricating an integrated circuit that offers security against reverse engineering using automatic pattern recognition.